1. Field of the Invention
The present invention relates to a delay locked loop, and more particularly, to a delay locked loop having a small jitter and a jitter reducing method thereof.
2. Description of the Related Art
In an I/O interfacing method that synchronizes data with a clock signal and transmits the synchronized data between a memory and a memory controller in a system, it is very important to correctly synchronize the data with the clock signal—particularly when a bus load increases and a transmission frequency rises. To synchronize data with a clock signal, a phase locked loop and/or a delay locked loop may be used. In general, a memory device synchronizes data with a clock signal using a delay locked loop.
FIG. 1 shows a block diagram of a conventional register-controlled type delay locked loop generally corresponding with a block diagram disclosed in U.S. Patent Laid-Open Publication No. 2006/001465 A1. Referring to FIG. 1, the register-controlled type delay locked loop includes a buffer 11, a coarse delay line 12, a phase selector 13, a phase blender 14, a phase detector 15, and a control circuit 16. The register-controlled type delay locked loop has a coarse/fine loop structure. The coarse delay line 12—in the form of a tapped delay line—is used as a coarse loop. As for the fine loop structure, the phase blender 14 is used. The operation of the delay locked loop to reduce a phase error will be explained in further detail below.
The control circuit 16 generates an UP/DOWN signal in response to a lead/lag state using phase error information (a signal corresponding to a phase difference between a clock signal CLK and a feedback signal OCLK) detected by the phase detector 15. The coarse delay line 12 receives the clock signal CLK through the buffer 11 and sequentially delays the clock signal CLK by a unit delay time to output a plurality of delayed signals. The phase selector 13 selects two delayed signals φi and φj from the plurality of delayed signals. The two delayed signals φi and φj originate from two neighboring unit coarse delay cells among a plurality of unit coarse delay cells included in the coarse delay line 12.
Delayed signals φi (i=0, 2, 4, . . . ) are signals output from even-numbered delay cells from among the unit coarse delay cells in the coarse delay line 12. Similarly, delayed signals φj (j=1, 3, 5, . . . ) are signals output from odd-numbered delay cells from among the unit coarse delay cells in the coarse delay line 12.
The phase blender 14 phase-blends the two delayed signals φi and φj for fine locking and outputs the final output signal OCLK having minimum phase error.
In the conventional delay locked loop, however, bang-bang jitter increases, as illustrated in FIG. 2, when the two delayed signal φi and φj are phase-blended near the edge of the delayed signal φi or the edge of the delayed signal φj. Accordingly, a need exists for a delay locked loop which is capable of reducing bang-bang jitter.